1. Field of the Invention
The present invention relates to a semiconductor device such as a large scale integrated circuit and a method for fabricating the same, and more particularly, to a semiconductor device fabricated using wafer-level chip-scale packaging technology and a method for fabricating the same.
2. Description of the Related Art
In recent years, electronic devices such as handheld devices or digital cameras have been reduced in size. This leads to a strong demand for reducing the size of each of semiconductor chips used for the electronic devices, which are mounted on boards such as a circuit board and an interposer, in order to achieve a high packaging density on the board. Wafer-level chip-scale packaging technology (hereinafter also referred to as “W-CSP”) has been used to achieve high packaging density. The W-CSP is the technology of packaging an integrated circuit at wafer level before singulating a wafer into individual dies, thus enabling the package size to be practically of the same as the die. A W-CSP structure includes metal interconnects and electrode terminals (e.g., solder bumps or solder coats) for external connection. Each metal interconnect extends from one of electrode pads formed on a wafer by wafer processing, to one of the electrode terminals. The metal interconnects are typically formed on patterned metal seed layers by electroplating. This step of forming the metal interconnects is called the pad redistribution. The pad redistribution enables the increase of the distance between the centers of adjacent electrode terminals formed at the outer side of the W-CSP structure without difficulty, thereby reducing the wiring density of the board on which the W-CSP structure is mounted. The W-CSP is disclosed in, for example, Japanese Patent Application Publication No. 2008-021849.
Before the pad redistribution in a fabrication process using the W-CSP, a wafer inspection may be performed using a probe machine (also referred to as “a prober”) that includes probe needles. Specifically, before the wafer inspection and its subsequent pad redistribution, wafer processing is employed to form, on a single wafer, semiconductor integrated circuits having electrode pads on their outer surfaces. The prober can be used to measure the electric characteristics of the semiconductor integrated circuits using the probe needles whose tips are brought in contact with the exposed surfaces of the electrode pads, thereby to determine whether the semiconductor integrated circuits are good or bad for wafer sort. The wafer inspection, however, may create residues (e.g., debris from the electrode pads) remaining on the electrode pads by bringing the probe needles in contact with the electrode pads. The residues may lead to cracks in dielectric films formed on the electrode pads in the pad redistribution step. The cracks may cause any damage such as short-circuiting to semiconductor chips.